1. Field of the Invention
The invention relates to a method for fabricating a capacitor in an integrated circuit (IC), and more particular to a method for fabricating a capacitor in a random dynamic access memory (DRAM) by using a tantalum oxide nitride (TaO.sub.x N.sub.y) layer as a barrier layer.
2. Description of the Related Art
In a DRAM, the typical method to access data is by charging or discharging optionally into each capacitor of the capacitor array on the semiconductor substrate.
Due to the higher and higher integration of IC, dimensions of devices or structures (such as transistors, capacitors) become smaller and smaller. Thus, the storage of charges (that is, the capacitance) of the capacitor in the design of a conventional planar capacitor decreases. The decrease of charge storage causes various problems, including mechanical deterioration and charge leakage by the larger susceptibility, and therefore, causes potential loss. The charge leakage caused by larger susceptibility may cause more frequent refresh period, and by which, memory can not handle data saving and reading properly. Moreover, the decrease of charge storage may need more complex data reading plan, or more sensitive charge induction amplifier.
Up to now, there are three ways to solve the problem of the decrease of capacitance of a capacitor due to the higher integration in a very large scaled integrated circuit. The first method is to reduce the thickness of the dielectric layer between two conductors of the capacitor. It is known that the capacitance is proportional to the inverse of distance between two conductors in a capacitor. Thus, the decrease of the thickness of dielectric layer can increase the capacitance effectively. However, according to the consideration of the uniformity and stability of the dielectric layer, this is a method difficult to control. The second method is to increase the surface area of the storage node of the capacitor. The capacitance is proportional to the surface area of storage node, that is, the conductor (electrode). Therefore, to increase the surface area of the storage node can increase the capacitance as well. The very common structure for increasing the surface area is the fin-shape or box-shape structure. These kinds of structures are complex for fabrication, and thus, cause the difficulty in mass production. The third method, which is the most direct method, is to adapt the material with high dielectric constant, such as, tantalum oxide (Ta.sub.2 O.sub.5), as the dielectric layer.
FIG. 1a and FIG. 1b are sectional views of the capacitor with a tantalum oxide as the dielectric layer fabricated by the conventional method. Referring to FIG. 1a, a tantalum oxide layer 12 is formed on a polysilicon layer 10 which is used as the bottom electrode in the capacitor. Meanwhile, the structure of the tantalum oxide layer 12 is amorphous. Thus, due to the high concentration of defects, a very high leakage current is occurred. Therefore, an annealing step is performed for the re-arrangement of tantalum oxide layer 12. It is normally carried out in a nitrogen monoxide (N.sub.2 O) environment. Referring to FIG. 1b, due to the very thin thickness of the tantalum oxide 12, during the annealing process, oxygen will penetrate through the tantalum oxide layer 12, and react with the polysilicon layer 10 to form a thin silicon oxide (SiO.sub.2) layer 14 between the tantalum oxide layer 12 and the polysilicon layer 10. It has been mentioned that the capacitance is proportional to the inverse of distance between two electrodes. Thus, although a material with very high dielectric constant is in use for the capacitor, the capacitor is degraded by another reason, that is, the increase thickness of the dielectric layer, silicon oxide layer 14.
Another integrated circuit structure, metal-insulator-metal (MIM) structure, is shown in FIG. 2a and FIG. 2b. Referring to FIG. 2a, a tantalum oxide layer 24 is formed on a polysilicon layer 20 covered by a metal layer 22. As mentioned above, the tantalum oxide is still an amorphous structure. An annealing process is necessary for the rearrangement. Similarly, while annealing, oxygen will penetrate through tantalum oxide layer 24 and approach the surface of the metal layer 22. The silicon atom in the polysilicon layer 20 will diffuse through the metal layer 22, and combine with the penetrated oxygen to form a silicon oxide layer 26. Again, the increment of thickness by the additional silicon oxide layer between the tantalum oxide layer 24 and the metal layer 22 cause a reduction of the capacitance.